BWC=BWC_0, DREQ=DREQ_0, ESG=ESG_0, INTMAJOR=INTMAJOR_0, MAJORELINK=MAJORELINK_0, INTHALF=INTHALF_0, START=START_0
TCD Control and Status
| START | Channel Start 0 (START_0): The channel is not explicitly started. 1 (START_1): The channel is explicitly started via a software initiated service request. |
| INTMAJOR | Enable an interrupt when major iteration count completes. 0 (INTMAJOR_0): The end-of-major loop interrupt is disabled. 1 (INTMAJOR_1): The end-of-major loop interrupt is enabled. |
| INTHALF | Enable an interrupt when major counter is half complete. 0 (INTHALF_0): The half-point interrupt is disabled. 1 (INTHALF_1): The half-point interrupt is enabled. |
| DREQ | Disable Request 0 (DREQ_0): The channel’s ERQ bit is not affected. 1 (DREQ_1): The channel’s ERQ bit is cleared when the major loop is complete. |
| ESG | Enable Scatter/Gather Processing 0 (ESG_0): The current channel’s TCD is normal format. 1 (ESG_1): The current channel’s TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. |
| MAJORELINK | Enable channel-to-channel linking on major loop complete 0 (MAJORELINK_0): The channel-to-channel linking is disabled. 1 (MAJORELINK_1): The channel-to-channel linking is enabled. |
| ACTIVE | Channel Active |
| DONE | Channel Done |
| MAJORLINKCH | Major Loop Link Channel Number |
| BWC | Bandwidth Control 0 (BWC_0): No eDMA engine stalls. 2 (BWC_2): eDMA engine stalls for 4 cycles after each R/W. 3 (BWC_3): eDMA engine stalls for 8 cycles after each R/W. |